since lef already specifies geometric constraints, what stops foundries from encoding all manufacturable geometry constraints solely within lef files so as to not have a non-standard design rule manual. similar for lib and electrical properties.
is there a technical reason for the lef standard to not be able to encode all types of drm rules?
"be extended" ... well if you go with extension then everything is possible ... of course. you could extend LEF with a turing complete language.
But as the current spec, it's not even close to being able to describe DRC rules ... it can barely even describe the min subset for routing ... even then some of the rules described in the LEF are not the actual rule but some more restrictive variation because you can't describe the actual rule.
just seems weird that signoff drc checking is one of the only things that doesn't yet have a 'dominant' standard/format and is still shipped as a manual that you implement
Started thinking about this after looking at:-
https://gitlab.com/Chips4Makers/PDKMaster
and how difficult it would be to have a standard framework (if you could encode a process and then describe errors using a theorem prover like lean)
Tools for managing and converting micro-electronics PDKs (process design kits)
rahulbhagwat
just seems weird that signoff drc checking is one of the only things that doesn't yet have a 'dominant' standard/format and is still shipped as a manual that you implement
The dominant standard format for DRC decks is Mentor Calibre decks, a proprietary format.
rahulbhagwat
Started thinking about this after looking at:-
https://gitlab.com/Chips4Makers/PDKMaster
and how difficult it would be to have a standard framework (if you could encode a process and then describe errors using a theorem prover like lean)
It is unclear how the tecnology abstraction I use now will be able to handle the more complex design rules you get from 65nm on. For open source PDKs we are still in the era of 'easy/simple' design rules.
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